1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a command buffer circuit of a semiconductor apparatus.
2. Related Art
There are various known ways to control the memory areas of the plurality of memory chips in a semiconductor apparatus.
A rank structure is one way to separate the memory areas. A single rank structure recognizes the memory areas as one to control the memory areas as one. A multi-rank structure recognizes the memory areas as two or more to separately control the multiple number of the memory areas.
A semiconductor apparatus operates in response to various external commands such as the clock enable commands and the impedance calibration commands.
The command signals for these external commands are received by a command buffer circuit in a semiconductor apparatus.
Referring to FIG. 1A, a semiconductor apparatus of a single rank structure utilizes a command buffer circuit 10 having two buffers 11, 12 for buffing the command signals such as one clock enable signal CKE and one impedance calibration signal ODT and generating the command control signals CKE_CTRL<0:N>, ODT_CTRL<0:N>.
However, now referring to FIG. 1B, a command buffer circuit 20 in a “multi-rank” semiconductor apparatus of two or four ranks controls the memory areas by distinguishing the two or four rank structure. As shown in FIG. 2B, there are four buffers 21, 22, 23, 24 in the command buffer circuit 20 for buffing the first and second clock enable signals CKE0, CKE1 and the first and second impedance calibration signals ODT0, ODT1 and generating the command control signals CKE0_CTRL<0:N>, CKE1_CTRL<0:N>, ODT0_CTRL<0:N>, ODT1_CTRL<0:N>.
A rank among the multiple ranks can be commanded to activate a clock signal with the first and second clock enable signals CKE0, CKE1 combined.
Furthermore, a rank among the multiple ranks can be commanded to perform an impedance calibration with the first and second impedance calibration signals ODT0, ODT1 combined.
Each of the buffers 11, 12, 21, 22, 23, 24 of FIGS. 1A-1B may be substantially identical to each other.
As described above, the configurations of the conventional command buffer circuits 10, 20 are different for the different rank structure, that is, the single vs. multi rank structure.
The command buffer circuit 10 configured for the single rank structure cannot be used in a multi-rank structure, and the command buffer circuit 20 configured for the multi-rank structure cannot be used in a single rank structure.
Furthermore, in spite of the multi-rank structure, it may be possible to use only one clock enable signal and one impedance calibration signal using a signal for selecting one of a plurality of memory chips.